//
// Generated by NVIDIA NVVM Compiler
//
// Compiler Build ID: UNKNOWN
// Unknown Toolkit Version
// Based on NVVM 7.0.1
//

.version 9.2
.target sm_120, texmode_independent
.address_size 64

	// .globl	DynamicKernel_nop_Sqrt_fmul_fsub_fsub

.entry DynamicKernel_nop_Sqrt_fmul_fsub_fsub(
	.param .u64 .ptr .global .align 8 DynamicKernel_nop_Sqrt_fmul_fsub_fsub_param_0,
	.param .u64 .ptr .global .align 8 DynamicKernel_nop_Sqrt_fmul_fsub_fsub_param_1,
	.param .u64 .ptr .global .align 8 DynamicKernel_nop_Sqrt_fmul_fsub_fsub_param_2,
	.param .u64 .ptr .global .align 8 DynamicKernel_nop_Sqrt_fmul_fsub_fsub_param_3,
	.param .u64 .ptr .global .align 8 DynamicKernel_nop_Sqrt_fmul_fsub_fsub_param_4
)
{
	.reg .pred 	%p<71>;
	.reg .b32 	%r<10>;
	.reg .f64 	%fd<78>;
	.reg .b64 	%rd<32>;


	ld.param.u64 	%rd10, [DynamicKernel_nop_Sqrt_fmul_fsub_fsub_param_0];
	ld.param.u64 	%rd11, [DynamicKernel_nop_Sqrt_fmul_fsub_fsub_param_1];
	ld.param.u64 	%rd12, [DynamicKernel_nop_Sqrt_fmul_fsub_fsub_param_2];
	ld.param.u64 	%rd13, [DynamicKernel_nop_Sqrt_fmul_fsub_fsub_param_3];
	ld.param.u64 	%rd14, [DynamicKernel_nop_Sqrt_fmul_fsub_fsub_param_4];
	mov.b32 	%r2, %envreg3;
	cvt.s64.s32 	%rd15, %r2;
	mov.u32 	%r3, %ntid.x;
	mov.u32 	%r4, %ctaid.x;
	mul.wide.s32 	%rd16, %r3, %r4;
	mov.u32 	%r5, %tid.x;
	cvt.s64.s32 	%rd17, %r5;
	add.s64 	%rd18, %rd17, %rd15;
	add.s64 	%rd1, %rd18, %rd16;
	cvt.u32.u64 	%r1, %rd1;
	setp.gt.s32 	%p2, %r1, 4;
	shl.b64 	%rd19, %rd1, 32;
	shr.s64 	%rd20, %rd19, 29;
	add.s64 	%rd2, %rd14, %rd20;
	mov.f64 	%fd67, 0d7FFFFFFFE0000000;
	@%p2 bra 	$L__BB0_2;

	ld.global.f64 	%fd67, [%rd2];

$L__BB0_2:
	abs.f64 	%fd35, %fd67;
	setp.gtu.f64 	%p3, %fd35, 0d7FF0000000000000;
	or.pred  	%p4, %p3, %p2;
	selp.f64 	%fd68, 0d0000000000000000, 0d7FFFFFFFE0000000, %p3;
	@%p4 bra 	$L__BB0_4;

	ld.global.f64 	%fd68, [%rd2];

$L__BB0_4:
	add.s64 	%rd3, %rd13, %rd20;
	mov.f64 	%fd69, 0d7FFFFFFFE0000000;
	@%p2 bra 	$L__BB0_6;

	ld.global.f64 	%fd69, [%rd3];

$L__BB0_6:
	abs.f64 	%fd37, %fd69;
	setp.gtu.f64 	%p6, %fd37, 0d7FF0000000000000;
	@%p6 bra 	$L__BB0_24;
	bra.uni 	$L__BB0_7;

$L__BB0_24:
	mov.f64 	%fd49, 0d0000000000000000;
	sub.f64 	%fd71, %fd49, %fd68;
	bra.uni 	$L__BB0_25;

$L__BB0_7:
	mov.f64 	%fd70, 0d7FFFFFFFE0000000;
	@%p2 bra 	$L__BB0_9;

	ld.global.f64 	%fd70, [%rd3];

$L__BB0_9:
	setp.lt.f64 	%p8, %fd68, 0d0000000000000000;
	setp.lt.f64 	%p9, %fd70, 0d0000000000000000;
	and.pred  	%p10, %p8, %p9;
	@%p10 bra 	$L__BB0_11;

	setp.leu.f64 	%p11, %fd70, 0d0000000000000000;
	setp.leu.f64 	%p12, %fd68, 0d0000000000000000;
	or.pred  	%p13, %p12, %p11;
	@%p13 bra 	$L__BB0_23;

$L__BB0_11:
	setp.eq.f64 	%p14, %fd70, %fd68;
	mov.f64 	%fd71, 0d0000000000000000;
	@%p14 bra 	$L__BB0_25;

	setp.eq.f64 	%p15, %fd70, 0d0000000000000000;
	setp.eq.f64 	%p16, %fd68, 0d0000000000000000;
	or.pred  	%p17, %p16, %p15;
	@%p17 bra 	$L__BB0_23;

	sub.f64 	%fd40, %fd70, %fd68;
	abs.f64 	%fd10, %fd40;
	{
	.reg .b32 %temp; 
	mov.b64 	{%temp, %r6}, %fd10;
	}
	and.b32  	%r7, %r6, 2146435072;
	setp.eq.s32 	%p18, %r7, 2146435072;
	@%p18 bra 	$L__BB0_23;

	abs.f64 	%fd11, %fd70;
	mul.f64 	%fd41, %fd11, 0d3D30000000000000;
	setp.gt.f64 	%p19, %fd10, %fd41;
	@%p19 bra 	$L__BB0_23;

	abs.f64 	%fd12, %fd68;
	mul.f64 	%fd42, %fd12, 0d3D30000000000000;
	setp.gt.f64 	%p20, %fd10, %fd42;
	@%p20 bra 	$L__BB0_23;

	setp.gtu.f64 	%p21, %fd10, 0d433FFFFFFFFFFFFF;
	@%p21 bra 	$L__BB0_22;

	cvt.rzi.s64.f64 	%rd4, %fd10;
	setp.gt.s64 	%p22, %rd4, 9007199254740991;
	@%p22 bra 	$L__BB0_22;

	cvt.rn.f64.s64 	%fd43, %rd4;
	setp.ne.f64 	%p23, %fd10, %fd43;
	setp.gtu.f64 	%p24, %fd11, 0d433FFFFFFFFFFFFF;
	or.pred  	%p25, %p23, %p24;
	@%p25 bra 	$L__BB0_22;

	cvt.rzi.s64.f64 	%rd5, %fd11;
	setp.gt.s64 	%p26, %rd5, 9007199254740991;
	@%p26 bra 	$L__BB0_22;

	cvt.rn.f64.s64 	%fd44, %rd5;
	setp.ne.f64 	%p27, %fd11, %fd44;
	setp.gtu.f64 	%p28, %fd12, 0d433FFFFFFFFFFFFF;
	or.pred  	%p29, %p27, %p28;
	@%p29 bra 	$L__BB0_22;

	cvt.rzi.s64.f64 	%rd23, %fd12;
	setp.lt.s64 	%p30, %rd23, 9007199254740992;
	cvt.rn.f64.s64 	%fd45, %rd23;
	setp.equ.f64 	%p31, %fd12, %fd45;
	and.pred  	%p32, %p30, %p31;
	@%p32 bra 	$L__BB0_23;

$L__BB0_22:
	mul.f64 	%fd47, %fd11, 0d3CF0000000000000;
	setp.lt.f64 	%p33, %fd10, %fd47;
	mul.f64 	%fd48, %fd12, 0d3CF0000000000000;
	setp.lt.f64 	%p34, %fd10, %fd48;
	and.pred  	%p35, %p33, %p34;
	@%p35 bra 	$L__BB0_25;

$L__BB0_23:
	sub.f64 	%fd71, %fd70, %fd68;

$L__BB0_25:
	add.s64 	%rd6, %rd12, %rd20;
	mov.f64 	%fd72, 0d7FFFFFFFE0000000;
	@%p2 bra 	$L__BB0_27;

	ld.global.f64 	%fd72, [%rd6];

$L__BB0_27:
	abs.f64 	%fd51, %fd72;
	setp.gtu.f64 	%p37, %fd51, 0d7FF0000000000000;
	or.pred  	%p38, %p37, %p2;
	selp.f64 	%fd73, 0d0000000000000000, 0d7FFFFFFFE0000000, %p37;
	@%p38 bra 	$L__BB0_29;

	ld.global.f64 	%fd73, [%rd6];

$L__BB0_29:
	add.s64 	%rd7, %rd11, %rd20;
	mov.f64 	%fd74, 0d7FFFFFFFE0000000;
	@%p2 bra 	$L__BB0_31;

	ld.global.f64 	%fd74, [%rd7];

$L__BB0_31:
	abs.f64 	%fd53, %fd74;
	setp.gtu.f64 	%p40, %fd53, 0d7FF0000000000000;
	@%p40 bra 	$L__BB0_49;
	bra.uni 	$L__BB0_32;

$L__BB0_49:
	mov.f64 	%fd65, 0d0000000000000000;
	sub.f64 	%fd76, %fd65, %fd73;
	bra.uni 	$L__BB0_50;

$L__BB0_32:
	mov.f64 	%fd75, 0d7FFFFFFFE0000000;
	@%p2 bra 	$L__BB0_34;

	ld.global.f64 	%fd75, [%rd7];

$L__BB0_34:
	setp.lt.f64 	%p42, %fd73, 0d0000000000000000;
	setp.lt.f64 	%p43, %fd75, 0d0000000000000000;
	and.pred  	%p44, %p42, %p43;
	@%p44 bra 	$L__BB0_36;

	setp.leu.f64 	%p45, %fd75, 0d0000000000000000;
	setp.leu.f64 	%p46, %fd73, 0d0000000000000000;
	or.pred  	%p47, %p46, %p45;
	@%p47 bra 	$L__BB0_48;

$L__BB0_36:
	setp.eq.f64 	%p48, %fd75, %fd73;
	mov.f64 	%fd76, 0d0000000000000000;
	@%p48 bra 	$L__BB0_50;

	setp.eq.f64 	%p49, %fd75, 0d0000000000000000;
	setp.eq.f64 	%p50, %fd73, 0d0000000000000000;
	or.pred  	%p51, %p50, %p49;
	@%p51 bra 	$L__BB0_48;

	sub.f64 	%fd56, %fd75, %fd73;
	abs.f64 	%fd25, %fd56;
	{
	.reg .b32 %temp; 
	mov.b64 	{%temp, %r8}, %fd25;
	}
	and.b32  	%r9, %r8, 2146435072;
	setp.eq.s32 	%p52, %r9, 2146435072;
	@%p52 bra 	$L__BB0_48;

	abs.f64 	%fd26, %fd75;
	mul.f64 	%fd57, %fd26, 0d3D30000000000000;
	setp.gt.f64 	%p53, %fd25, %fd57;
	@%p53 bra 	$L__BB0_48;

	abs.f64 	%fd27, %fd73;
	mul.f64 	%fd58, %fd27, 0d3D30000000000000;
	setp.gt.f64 	%p54, %fd25, %fd58;
	@%p54 bra 	$L__BB0_48;

	setp.gtu.f64 	%p55, %fd25, 0d433FFFFFFFFFFFFF;
	@%p55 bra 	$L__BB0_47;

	cvt.rzi.s64.f64 	%rd8, %fd25;
	setp.gt.s64 	%p56, %rd8, 9007199254740991;
	@%p56 bra 	$L__BB0_47;

	cvt.rn.f64.s64 	%fd59, %rd8;
	setp.ne.f64 	%p57, %fd25, %fd59;
	setp.gtu.f64 	%p58, %fd26, 0d433FFFFFFFFFFFFF;
	or.pred  	%p59, %p57, %p58;
	@%p59 bra 	$L__BB0_47;

	cvt.rzi.s64.f64 	%rd9, %fd26;
	setp.gt.s64 	%p60, %rd9, 9007199254740991;
	@%p60 bra 	$L__BB0_47;

	cvt.rn.f64.s64 	%fd60, %rd9;
	setp.ne.f64 	%p61, %fd26, %fd60;
	setp.gtu.f64 	%p62, %fd27, 0d433FFFFFFFFFFFFF;
	or.pred  	%p63, %p61, %p62;
	@%p63 bra 	$L__BB0_47;

	cvt.rzi.s64.f64 	%rd28, %fd27;
	setp.lt.s64 	%p64, %rd28, 9007199254740992;
	cvt.rn.f64.s64 	%fd61, %rd28;
	setp.equ.f64 	%p65, %fd27, %fd61;
	and.pred  	%p66, %p64, %p65;
	@%p66 bra 	$L__BB0_48;

$L__BB0_47:
	mul.f64 	%fd63, %fd26, 0d3CF0000000000000;
	setp.lt.f64 	%p67, %fd25, %fd63;
	mul.f64 	%fd64, %fd27, 0d3CF0000000000000;
	setp.lt.f64 	%p68, %fd25, %fd64;
	and.pred  	%p69, %p67, %p68;
	@%p69 bra 	$L__BB0_50;

$L__BB0_48:
	sub.f64 	%fd76, %fd75, %fd73;

$L__BB0_50:
	mul.f64 	%fd31, %fd71, %fd76;
	setp.lt.f64 	%p70, %fd31, 0d0000000000000000;
	mov.f64 	%fd77, 0d7FF80000000001F6;
	@%p70 bra 	$L__BB0_52;

	sqrt.rn.f64 	%fd77, %fd31;

$L__BB0_52:
	add.s64 	%rd31, %rd10, %rd20;
	st.global.f64 	[%rd31], %fd77;
	ret;

}

  